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| exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com XRT86VX38 octal t1/e1/j1 framer/liu combo - hardware description june 2009 rev. 1.0.1 general description the XRT86VX38 is an eight-channel 1.544 mbit/s or 2.048 mbit/s ds1/e1/j1 framer and long-haul/short- hual liu integrated solution featuring r 3 technology (relayless, reconfigurable, redundancy) and bits timing element. the physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86VX38 provides protection from power failures and hot swapping. the XRT86VX38 contains an integrated ds1/e1/j1 framer and liu which provide ds1/e1/j1 framing and error accumulation in accordance with ansi/itu_t specifications. each framer has its own framing synchronizer and transmit-receive slip buffers. the slip buffers can be independently enabled or disabled as required and can be configured to frame to the common ds1/e1/j1 signal formats. each framer block contains its own transmit and receive t1/e1/j1 framing function. there are 3 transmit hdlc controlle rs per channel which encapsulate contents of the transmit hdlc buffers into lapd message frames. there are 3 receive hdlc controllers per channel which extract the payload content of receive lapd message frames from the incoming t1/e1/j1 data stream and write the contents into the receive hdlc buffers. each framer also contains a transmit and overhead data input port, which permits data link terminal equipment direct access to the outbound t1/e1/j1 frames. likewise, a receive overhead output data port permits data link terminal equipment direct access to the data link bits of the inbound t1/e1/j1 frames. the XRT86VX38 fully meets a ll of the latest t1/e1/j1 specifications: ansi t1/e1.107-1988, ansi t1/ e1.403-1995, ansi t1/e1.231-1993, ansi t1/ e1.408-1990, at&t tr 62411 (12-90) tr54016, and itu g-703, g.704, g706 and g.733, at&t pub. 43801, and ets 300 011, 300 233, jt g.703, jt g.704, jt g706, i.431. extensive test and diagnostic functions include loop-backs, boundary scan, pseudo random bit sequence (prbs) test pattern generation, performance monitor, bit error rate (ber) meter, forced error insertion, and lapd unchannelized data payload processing according to itu-t standard q.921. applications and features (next page) f igure 1. XRT86VX38 8- channel ds1 (t1/e1/j1) f ramer /liu c ombo performance monitor prbs generator & analyser hdlc/lapd controllers liu & loopback control dma interface signaling & alarms jtag wr ale_as rd rdy_dtack ? p select a[14:0] d[ 7: 0] microprocessor interface 4 3 tx serial clock rx serial clock 8khz sync osc back plane 1.544-16.384 mbit/s local pcm highway st-bus 2-frame slip buffer elastic store tx serial data in tx liu interface 2-frame slip buffer elastic store rx liu interface rx framer rx serial data out rtip rring ttip tring external data link controller tx overhead in rx overhead out XRT86VX38 1 of 8-channels tx framer llb lb system (terminal) side line side 1:1 turns ratio 1:2 turns ratio memory intel/motorola p configuration , control & status monitor rxlos txon int
XRT86VX38 2 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 applications ? high-density t1/e1/j1 in terfaces for multiplexe rs, switches, lan routers and digital modems ? sonet/sdh terminal or add/ drop multiplexers (adms) ? t1/e1/j1 add/drop multiplexers (mux) ? channel service units (csus): t1/e1/j1 and fractional t1/e1/j1 ? bits timing ? digital access cross-connect system (dacs) ? digital cross-connect systems (dcs) ? frame relay switches and access devices (frads) ? isdn primary rate interfaces (pra) ? pbxs and pcm channel bank ? t3 channelized access concentrators and m13 mux ? wireless base stations ? atm equipment with inte grated ds1 interfaces ? multichannel ds1 test equipment ? t1/e1/j1 performance monitoring ? voice over packet gateways ? routers features ? supports section 13 - synchronization interface in itu g.703 for both transmit and receive paths ? supports ssm synchronous messaging generation (boc fo r t1, national bits for e1) on the transmit path ? supports ssm synchronous messaging extraction (boc fo r t1, national bits for e1) on the receive path ? supports bits timing generation on the transmit outputs ? supports bits timing extraction from nrz data on the analog receive path ? ds-0 monitoring on both transmit and receive time slots ? supports ssm synchronization messaging per ansi t1.101-1999 and itu g.704 ? supports a customized section 13 - synchronization interface in g.703 at 1.544mhz ? independent, full duplex ds1 tx and rx framer/lius ? each channel has full featured long-haul/short-haul liu ? two 512-bit (two-frame) elastic store, pcm frame slip bu ffers (fifo) on tx and rx provide up to 8.192 mhz asynchronous back plane connections with jitter and wander attenuation ? supports input pcm and signaling data at 1.544, 2.04 8, 4.096 and 8.192 mbits. also supports 2-channel multiplexed 12.352/16.384 (hmvip/h .100) mbit/s on the back plane bus ? programmable output clocks for fractional t1/e1/j1 ? supports channel associated signaling (cas) ? supports common channel signalling (ccs) ? supports isdn primary rate in terface (isdn pri) signaling XRT86VX38 3 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description ? extracts and inserts robbed bit signaling (rbs) ? 3 integrated hdlc controllers for transmit and receive, each controller having two 96-byte buffers (buffer 0 / buffer 1) ? hdlc controllers support ss7 ? timeslot assignable hdlc ? v5.1 or v5.2 interface ? automatic performance report generation (pmon status) can be inserted into the transmit lapd interface every 1 second or for a single transmission ? supports sprm and nprm ? alarm indication signal with customer installation signature (ais-ci) ? remote alarm indication with cu stomer installation (rai-ci) ? gapped clock interface mode for transmit and receive. ? intel/motorola and power pc interfaces for configuration, control and status monitoring ? parallel search algorithm for fast frame synchronization ? wide choice of t1 framing structures: sf/d4, esf, slc ? 96, t1dm and n-frame (non-signaling) ? direct access to d and e c hannels for fast transmission of data link information ? full bert controller for generation and dete ction on system and line side of the chip ? prbs, qrss, and network loop code generation and detection ? seven independent, simultaneous loop code detectors per channel ? programmable interrupt output pin ? supports programmed i/o and dma modes of read-write access ? the framer block encodes and decodes the t1/e1/j1 frame serial data ? detects and forces red (sai), yellow (rai) and blue (ais) alarms ? detects oof, lof, los errors and cofa conditions ? loopbacks: local (llb) and line remote (lb) ? facilitates inverse mu ltiplexing for atm ? performance monitor wi th one second polling ? boundary scan (ieee 11 49.1) jtag test port ? accepts external 8khz sync reference ? 1.8v inner core ? 3.3v cmos operation wit h 5v tolerant inputs ? 256-pin fpbga and 329-pin fpbga package with -40 ? c to +85 ? c operation ordering information p art n umber p ackage o perating t emperature r ange XRT86VX38ib329 329 fine pitch ball grid array -40 ? c to +85 ? c XRT86VX38ib256 256 fine pitch ball grid array -40 ? c to +85 ? c XRT86VX38 4 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 329 ball - fine pitch ball grid array (b ottom view - see pin list for description) 19181716151413121110987654321 ooooooooooooooooooo a ooooooooooooooooooo b ooooooooooooooooooo c ooooooooooooooooooo d ooooooooooooooooooo e ooooo ooooo f ooooo ooooooo ooooo g ooooo ooooooo ooooo h ooooo ooooooo ooooo j ooooo ooooooo ooooo k ooooo ooooooo ooooo l ooooo ooooooo ooooo m ooooo ooooooo ooooo n ooooo ooooo p ooooooooooooooooooo r ooooooooooooooooooo t ooooooooooooooooooo u ooooooooooooooooooo v ooooooooooooooooooo w XRT86VX38 5 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description 256 ball - fine pitch ball grid array (b ottom view - see pin list for description) 16151413121110987654321 oooooooooooooooo a oooooooooooooooo b oooooooooooooooo c oooooooooooooooo d oooooooooooooooo e oooooooooooooooo f oooooooooooooooo g oooooooooooooooo h oooooooooooooooo j oooooooooooooooo k oooooooooooooooo l oooooooooooooooo m oooooooooooooooo n oooooooooooooooo p oooooooooooooooo r oooooooooooooooo t XRT86VX38 i octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 list of paragraphs 1.0 pin lists ................................................................................................................. ................................6 2.0 pin descriptions .......................................................................................................... ....................12 XRT86VX38 ii rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description list of figures figure 1.: XRT86VX38 8-channel ds1 (t1/e1/j1) framer/liu combo ................................................................ ............ 1 figure 2.: itu g.703 pulse template ...................... ..................................................................... ................................... 43 figure 3.: itu g.703 section 13 synchronous interface pu lse template .......................................................... ............. 44 figure 4.: dsx-1 pulse template (normalized amplitude) ........................................................................ ...................... 45 XRT86VX38 iii octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 list of tables table 1:: 329 ball list by ball number ................ ........................................................................ ....................................... 6 table 2:: 256 ball list by ball number ................ ........................................................................ ....................................... 9 table 3:: pin description structur e ........................................................................................... ....................................... 12 table 4:: e1 receiver electrical characteristics .... .......................................................................... ................................ 40 table 5:: t1 receiver electrical characteristics .... .......................................................................... ................................ 41 table 6:: e1 transmitter electrical characteristics ........................................................................... ............................... 41 table 7:: e1 transmit return loss requirement ......... ........................................................................ ............................ 42 table 8:: t1 transmitter electrical characteristics ........................................................................... ............................... 42 table 9:: transmit pulse mask specification ............ ....................................................................... ................................ 43 table 10:: e1 synchronous interface transmit pulse mask specification ....... .............. .............. ........... ........... .............. 44 table 11:: dsx1 interface isolated pulse mask and corner points ............................................................... ................... 45 table 12:: ac electrical characteristics .............. ........................................................................ ..................................... 46 XRT86VX38 6 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description 1.0 pin lists t able 1: 329 b all l ist by b all n umber p in p in n ame a1 vdd a2 vddpll18 a3 vss a4 dgnd a5 tdi a6 vss a7 rxsig0 a8 rxsync0 a9 txsync0 a10 txsig0 a11 rxserclk1 a12 vdd a13 txsync1 a14 txser1 a15 vss a16 rxcasync2 a17 rxcrcsync2 a18 rxsclk2 a19 vdd b1 gndpll b2 vddpll18 b3 vddpll18 b4 dvdd18 b5 rxtsel b6 vdd b7 tms b8 rxlos0 b9 vdd b10 txmsync0 b11 txserclk0 b12 rxsig1 b13 rxlos1 b14 txmsync1 b15 txsig1 b16 rxserclk2 b17 rxser2 b18 txsig2 b19 rxser3 c1 rtip0 c2 rvdd0 c3 gndpll c4 vddpll18 c5 vss c6 agnd c7 atest c8 mclkin c9 trst c10 tck c11 rxsclk0 c12 rxser1 c13 rxsync1 c14 rxcasync1 c15 rxsync2 c16 rxsig2 c17 txserclk2 c18 txmsync2 c19 rxcrcsync3 d1 rring0 d2 rgnd0 d3 ttip0 d4 tvdd0 d5 gndpll d6 avdd18 t able 1: 329 b all l ist by b all n umber p in p in n ame d7 tdo d8 rxser0 d9 rxserclk0 d10 rxcrcsync0 d11 txser0 d12 rxcrcsync1 d13 vdd18 d14 txserclk1 d15 rxlos2 d16 txsync2 d17 txser2 d18 rxsig3 d19 rxcasync3 e1 rtip1 e2 rvdd1 e3 tring0 e4 tgnd0 e5 analog e6 vdd18 e7 vss e8 vdd18 e9 vdd18 e10 rxcasync0 e11 vdd18 e12 vdd18 e13 vdd18 e14 rxsclk1 e15 vdd18 e16 vdd e17 rxsync3 e18 rxlos3 e19 txsync3 t able 1: 329 b all l ist by b all n umber p in p in n ame f1 rring1 f2 vss f3 ttip1 f4 tring1 f5 vdd f15 vdd18 f16 rxserclk3 f17 rxsclk3 f18 txserclk3 f19 txser3 g1 rvdd2 g2 rgnd1 g3 tgnd1 g4 tvdd1 g5 vdd18 g7 vdd18 g8 vss g9 vdd18 g10 vss g11 vdd18 g12 vss g13 vdd18 g15 data7 g16 txmsync3 g17 wr / r/ w g18 txsig3 g19 cs h1 rtip2 h2 rgnd2 h3 tring2 h4 ttip2 h5 vss t able 1: 329 b all l ist by b all n umber p in p in n ame XRT86VX38 7 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 h7 vss h8 vss h9 vss h10 vss h11 vss h12 vss h13 vss h15 addr12 h16 data6 h17 addr14 h18 data5 h19 addr13 j1 rring2 j2 rvdd3 j3 tgnd2 j4 tvdd2 j5 vdd18 j7 vdd18 j8 vss j9 vss j10 vss j11 vss j12 vss j13 vdd18 j15 addr11 j16 addr9 j17 vdd j18 int j19 data4 k1 rtip3 k2 rgnd3 k3 tring3 t able 1: 329 b all l ist by b all n umber p in p in n ame k4 ttip3 k5 tvdd3 k7 vss k8 vss k9 vss k10 vss k11 vss k12 vss k13 vss k15 addr8 k16 data2 k17 ale / as k18 addr10 k19 ptype2 l1 rring3 l2 rvdd4 l3 ttip4 l4 tring4 l5 tgnd3 l7 vdd18 l8 vss l9 vss l10 vss l11 vss l12 vss l13 vdd18 l15 vdd18 l16 addr4 l17 addr6 l18 data3 l19 addr7 m1 rtip4 t able 1: 329 b all l ist by b all n umber p in p in n ame m2 rgnd4 m3 tgnd4 m4 tvdd4 m5 vdd18 m7 vss m8 vss m9 vss m10 vss m11 vss m12 vss m13 vss m15 addr3 m16 rdy / dtack m17 addr1 m18 addr2 m19 addr5 n1 rring4 n2 rvdd5 n3 ttip5 n4 tring5 n5 tvdd5 n7 vdd18 n8 vss n9 vdd18 n10 vss n11 vdd18 n12 vss n13 vdd18 n15 vss n16 data0 n17 rd / ds / we n18 ptype1 t able 1: 329 b all l ist by b all n umber p in p in n ame n19 addr0 p1 rtip5 p2 vss p3 tgnd5 p4 rvdd6 p5 tgnd6 p15 vdd18 p16 vdd p17 ptype0 p18 pclk p19 data1 r1 rring5 r2 rgnd5 r3 tvdd6 r4 tring6 r5 ttip6 r6 vss r7 rxcrcsync7 r8 txmsync6 r9 vdd18 r10 vdd18 r11 vdd r12 vdd18 r13 vdd r14 vdd18 r15 vdd r16 req1 r17 rxserclk4 r18 vdd r19 ack1 t1 rtip6 t2 rgnd6 t able 1: 329 b all l ist by b all n umber p in p in n ame XRT86VX38 8 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description t3 ttip7 t4 tvdd7 t5 8kextosc t6 vdd18 t7 vdd t8 rxsync7 t9 rxcasync7 t10 rxsync6 t11 txserclk5 t12 rxserclk6 t13 txmsync5 t14 rxsclk5 t15 rxserclk5 t16 txsync4 t17 rxsync4 t18 ack0 t19 req0 u1 rring6 u2 rvdd7 u3 tring7 u4 vdd u5 txserclk7 u6 txsig7 u7 rxserclk7 u8 rxsclk7 u9 rxsig7 u10 txsig6 u11 rxsclk6 u12 vss u13 txsync5 u14 rxsync5 u15 rxlos5 t able 1: 329 b all l ist by b all n umber p in p in n ame u16 txmsync4 u17 rxcasync4 u18 rxsig4 u19 rxlos4 v1 vdd v2 tgnd7 v3 rgnd7 v4 reset v5 e1oscclk v6 txmsync7 v7 rxlos7 v8 rxser7 v9 txsync6 v10 rxcrcsync6 v11 rxlos6 v12 rxsig6 v13 txser5 v14 rxser5 v15 rxcasync5 v16 txsig4 v17 txserclk4 v18 rxser4 v19 rxcrcsync4 w1 vss w2 rtip7 w3 rring7 w4 txon w5 t1oscclk w6 txser7 w7 txsync7 w8 txserclk6 w9 txser6 t able 1: 329 b all l ist by b all n umber p in p in n ame w10 rxcasync6 w11 vdd w12 rxser6 w13 txsig5 w14 rxsig5 w15 vdd w16 rxcrcsync5 w17 txser4 w18 rxsclk4 w19 vss t able 1: 329 b all l ist by b all n umber p in p in n ame XRT86VX38 9 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 t able 2: 256 b all l ist by b all n umber p in p in n ame a1 gndpll a2 gndpll a3 vddpll18 a4 vddpll18 a5 rxtsel a6 tms a7 rxlos0 a8 rxcrcsync0 a9 rxcasync0 a10 rxserclk1 a11 rxsync1 a12 txmsync1 a13 rxsync2 a14 txsync2 a15 rxsclk2 a16 vdd b1 rtip0 b2 rvdd0 b3 vddpll18 b4 analog b5 agnd b6 tdo b7 rxser0 b8 rxserclk0 b9 rxsync0 b10 rxsclk0 b11 rxser1 b12 txsync1 b13 txserclk1 b14 rxser2 b15 txserclk2 b16 rxser3 c1 rring0 c2 rgnd0 c3 ttip0 c4 gndpll c5 avdd18 c6 dvdd18 c7 atest c8 tdi c9 txsync0 c10 rxcrcsync1 c11 rxlos1 c12 txser1 c13 rxserclk2 c14 rxcrcsync2 c15 txmsync2 c16 rxsync3 d1 rtip1 d2 rvdd1 d3 tring0 d4 tvdd0 d5 vddpll18 d6 dgnd d7 trst d8 tck d9 txmsync0 d10 txserclk0 d11 rxcasync1 d12 rxsclk1 d13 rxcasync2 d14 txser2 d15 rxserclk3 t able 2: 256 b all l ist by b all n umber p in p in n ame d16 rxlos3 e1 rring1 e2 rgnd1 e3 ttip1 e4 tring1 e5 tgnd0 e6 mclkin e7 vss e8 vdd e9 vss e10 txser0 e11 vdd e12 rxcrcsync3 e13 rxcasync3 e14 txmsync3 e15 txsync3 e16 txserclk3 f1 rtip2 f2 rvdd2 f3 tgnd1 f4 tvdd1 f5 tvdd2 f6 vss f7 vss f8 vdd18 f9 vdd18 f10 vdd18 f11 rxlos2 f12 rxsclk3 f13 wr / r/ w f14 cs f15 txser3 t able 2: 256 b all l ist by b all n umber p in p in n ame f16 addr13 g1 rring2 g2 rgnd2 g3 ttip2 g4 tring2 g5 tgnd2 g6 vdd18 g7 vss g8 vss g9 vss g10 vss g11 addr14 g12 data6 g13 data7 g14 data5 g15 vdd g16 addr12 h1 rtip3 h2 rvdd3 h3 ttip3 h4 tring3 h5 tvdd3 h6 vdd18 h7 vss h8 vss h9 vss h10 vss h11 vdd18 h12 ptype2 h13 data4 h14 addr10 h15 int t able 2: 256 b all l ist by b all n umber p in p in n ame XRT86VX38 10 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description h16 addr11 j1 rring3 j2 rgnd3 j3 ttip4 j4 tring4 j5 tgnd3 j6 vdd18 j7 vss j8 vss j9 vss j10 vss j11 vdd18 j12 data3 j13 addr9 j14 addr8 j15 addr7 j16 ale / as k1 rtip4 k2 rvdd4 k3 tgnd4 k4 tvdd4 k5 tvdd5 k6 vdd18 k7 vss k8 vss k9 vss k10 vss k11 vdd18 k12 data2 k13 addr4 k14 addr6 k15 addr2 t able 2: 256 b all l ist by b all n umber p in p in n ame k16 addr5 l1 rring4 l2 rgnd4 l3 ttip5 l4 tring5 l5 tgnd5 l6 8kextosc l7 vdd18 l8 vdd18 l9 vdd18 l10 vdd18 l11 addr3 l12 data1 l13 addr0 l14 addr1 l15 rd / ds / we l16 rdy / dtack m1 rtip5 m2 rvdd5 m3 ttip6 m4 tring6 m5 tvdd6 m6 vdd m7 rxsclk7 m8 rxcasync7 m9 vdd m10 rxserclk6 m11 txsync5 m12 ptype1 m13 ptype0 m14 data0 m15 ack1 t able 2: 256 b all l ist by b all n umber p in p in n ame m16 pclk n1 rring5 n2 rgnd5 n3 tgnd6 n4 tvdd7 n5 tgnd7 n6 txmsync7 n7 rxcrcsync7 n8 txsync6 n9 rxcasync6 n10 txserclk5 n11 rxsync5 n12 txser4 n13 rxsync4 n14 vdd n15 ack0 n16 req0 p1 rtip6 p2 rvdd6 p3 ttip7 p4 tring7 p5 txser7 p6 txserclk7 p7 rxlos7 p8 rxser7 p9 rxsclk6 p10 txser5 p11 rxser5 p12 rxlos5 p13 txmsync4 p14 rxserclk4 p15 rxser4 t able 2: 256 b all l ist by b all n umber p in p in n ame p16 rxlos4 r1 rring6 r2 rgnd6 r3 rgnd7 r4 reset r5 e1oscclk r6 rxserclk7 r7 rxsync7 r8 txmsync6 r9 rxcrcsync6 r10 rxlos6 r11 txmsync5 r12 rxcasync5 r13 rxcrcsync5 r14 rxcasync4 r15 rxcrcsync4 r16 req1 t1 rvdd7 t2 rtip7 t3 rring7 t4 txon t5 t1oscclk t6 txsync7 t7 txserclk6 t8 txser6 t9 rxsync6 t10 rxser6 t11 rxsclk5 t12 rxserclk5 t13 txsync4 t14 txserclk4 t15 rxsclk4 t able 2: 256 b all l ist by b all n umber p in p in n ame XRT86VX38 11 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 t16 vdd t able 2: 256 b all l ist by b all n umber p in p in n ame XRT86VX38 12 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description 2.0 pin descriptions there are six types of pins defined throughout this pin description and the corresponding symbol is presented in table below. the per-channel pin is indicated by the ch annel number or the letter ?n? which is appended at the end of the signal name, for example, txsern, where "n " indicates channels 0 to 7. all output pins are "tri- stated" upon hardware reset. the structure of the pin description is divided into eleven groups, as presented in the table below t able 3: p in d escription s tructure s ection p age n umber transmit system side inter - face page 13 receive system side inter - face page 18 receive line interface page 23 transmit line interface page 24 timing interface page 25 jtag interface page 26 microprocessor interface page 26 power pins (3.3v) page 35 power pins (1.8v) page 36 ground pins page 37 no connect pins page 38 s ymbol p in t ype i input o output i/o bidirectional gnd ground pwr power nc no connect XRT86VX38 13 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 transmit system side interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription txser0/ txpos0 txser1/ txpos1 txser2/ txpos2 txser3/ txpos3 txser4/ txpos4 txser5/ txpos5 txser6/ txpos6 txser7/ txpos7 d11 a14 d17 f19 w17 v13 w9 w6 e10 c12 d14 f15 n12 p10 t8 p5 i - transmit serial data input (txsern)/transmit positive digital input (txposn): the exact function of these pins depends on the mode of operation selected, as described below. ds1/e1 mode - txsern these pins function as the transmit serial data input on the system side interface, which are latched on the rising edge of the txserclkn pin. any payload data applied to this pin will be inserted into an outbound ds 1/e1 frame and output to the line. in ds1 mode, the framing alignment bits, facility data link bits, crc-6 bits, and signaling information can also be inserted from this input pin if configured appropriately. in e1 mode, all data intended to be transported via time slots 1 through 15 and time slots 17 through 31 must be applied to this input pin. data intended for time slots 0 and 16 can also be applied to this input pin if configured accordingly. ds1 or e1 high-speed multiplexed mode* - txsern in this mode, these pins are used as the high-speed multi - plexed data input pin on the system side. high-speed multi - plexed data of channels 0-3 must be applied to txser0 and high-speed multiplexed data of channels 4-7 must be applied to txser4 in a byte or bit-interleaved way. the framer latches in the multiplexed data on txser0 and txser4 using txm - sync/txinclk and demultiplexes this data into 4 serial streams. the liu block will th en output the data to the line interface using txserclkn. ds1 or e1 framer bypass mode - txposn in this mode, txsern is used for the positive digital input pin (txposn) to the liu. n ote : 1. *high-speed multiplexed modes include (for t1/e1) 16.384mhz hmvip, h.100, bit-multiplexed modes, and (for t1 only) 12.352mhz bit-multiplexed mode. 2. in ds1 high-speed modes, the ds-0 data is mapped into an e1 frame by ignoring every fourth time slot (don?t care). 3. these 8 pins are internally pulled ?high? for each channel. XRT86VX38 14 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description txserclk0/ txlineclk0 txserclk1/ txlineclk1 txserclk2/ txlineclk2 txserclk3/ txlineclk3 txserclk4/ txlineclk4 txserclk5/ txlineclk5 txserclk6/ txlineclk6 txserclk7/ txlineclk7 b11 d14 c17 f18 v17 t11 w8 u5 d10 b13 b15 e16 t14 n10 t7 p6 i/o 12 transmit serial clock (txserclkn)/transmit line clock (txserclkn): the exact function of these pins depends on the mode of operation selected, as described below. in base-rate mode (1.544 mhz/2.048mhz) - txserclkn: this clock signal is used by the transmit serial interface to latch the contents on the txsern pins into the t1/e1 framer on the rising edge of the txserclkn. these pins can be con - figured as input or output as described below. when txserclkn is configured as input: these pins will be inputs if the txserclk is chosen as the timing source for the transmit framer. users must provide a 1.544mhz clock rate to this input pin for t1 mode of operation, and 2.048mhz clock rate in e1 mode. when txserclkn is configured as output: these pins will be outputs if either the recovered line clock or the mclk pll is chosen as the timing source for the t1/e1 transmit framer. the transmit framer will output a 1.544mhz clock rate in t1 mode of operat ion, and a 2.048mhz clock rate in e1 mode. ds1/e1 high-speed backplane modes* - txserclkn as input only in this mode, txserclk is an optional clock signal input which is used as the timing sour ce for the transmit line inter - face, and is only required if txserclk is chosen as the tim - ing source for the transmit framer. if txserclk is chosen as the timing source, system equipment should provide 1.544mhz (for t1 mode) or 2.048mhz (for e1 mode) to the txserclkn pins on each channel. txserclk is not required if either the recovered clock or mclk pll is chosen as the timing source of the device. high speed or multiplexed data is latched into the device using the txmsync/txinclk high-speed clock signal. ds1 or e1 framer bypass mode - txlineclkn in this mode, txserclkn is us ed as the transmit line clock (txlineclk) to the liu. n ote : *high-speed backplane modes include (for t1/e1) 2.048mvip, 4.096mhz, 8.192mhz, 16.384mhz hmvip, h.100, bit-multip lexed modes, and (for t1 only) 12.352mhz bit-multiplexed mode. n ote : in ds1 high-speed modes, the ds-0 data is mapped into an e1 frame by ignoring every fourth time slot (don?t care). n ote : these 8 pins are internally pulled ?high? for each channel. transmit system side interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription XRT86VX38 15 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 txsync0/ txneg0 txsync1/ txneg1 txsync2/ txneg2 txsync3/ txneg3 txsync4/ txneg4 txsync5/ txneg5 txsync6/ txneg6 txsync7/ txneg7 a9 a13 d16 e19 t16 u13 v9 w7 c9 b12 a14 e15 t13 m11 n8 t6 i/o 12 transmit single frame sync pulse (txsyncn) / transmit negative digital input (txnegn): the exact function of these pins depends on the mode of operation selected, as described below. ds1/e1 base rate mode (1 .544mhz/2.048mhz) - txsyncn: these txsyncn pins are used to indicate the single frame boundary within an outbound t1/e1 frame. in both ds1 or e1 mode, the single frame boundary repeats every 125 microsec - onds (8khz). in ds1/e1 base rate, txsyncn can be configured as either input or output as described below. when txsyncn is configured as an input : users must provide a signal which must pulse "high" for one period of txserclk during the first bit of an outbound ds1/ e1 frame. it is imperative that the txsync input signal be syn - chronized with the txserclk input signal. when txsyncn is configured as an output: the transmit t1/e1 framer will output a signal which pulses "high" for one period of txserclk during the first bit of an outbound ds1/e1 frame. ds1/e1 high-speed backplane modes* - txsyncn as input only: in this mode, txsyncn must be an input regardless of the clock source that is chosen to be the timing source for the transmit framer. in 2.048mvip/4.096/8.192mhz high-speed modes, txsyncn pins must be pulsed ?high? for one period of txserclk during the first bit of the outbound t1/e1 frame. in hmvip mode, txsync0 and txsync4 must be pulsed ?high? for 4 clock cycles of the txmsync/txinclk signal in the position of the first two and the last two bits of a multiplexed frame. in h.100 mode, txsync0 and txsync4 must be pulsed ?high? for 2 clock cycles of the txmsync/txinclk sig - nal in the position of the first an d the last bit of a multiplexed frame. ds1 or e1 framer bypass mode - txnegn in this mode, txsyncn is used as the negative digital input pin (txneg) to the liu. n ote : *high-speed backplane modes include (for t1/e1) 2.048mvip, 4.096mhz, 8.192mhz, 16.384mhz hmvip, h.100, bit-multiplexed modes, and (for t1 only) 12.352mhz bit-multiplexed mode. n ote : in ds1 high-speed modes, the ds-0 data is mapped into an e1 frame by ignoring every fourth time slot (don?t care). n ote : these 8 pins are internally pulled ?low? for each channel. transmit system side interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription XRT86VX38 16 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description txmsync0/ txinclk0 txmsync1/ txinclk1 txmsync2/ txinclk2 txmsync3/ txinclk3 txmsync4/ txinclk4 txmsync5/ txinclk5 txmsync6/ txinclk6 txmsync7/ txinclk7 b10 b14 c18 g16 u16 t13 r8 v6 d9 a12 c15 e14 p13 r11 r8 n6 i/o 12 multiframe sync pulse (txmsyncn) / transmit input clock (txinclkn) the exact function of these pins depends on the mode of operation selected, as described below. ds1/e1 base rate mode (1.544mhz/2.048mhz) - txm - syncn in this mode, these pins are used to indicate the multi-frame boundary within an outbound ds1/e1 frame. in ds1 esf mode, txmsyncn repeats every 3ms. in ds1 sf mode, txmsyncn repeats every 1.5ms. in e1 mode, txmsyncn repeats every 2ms. if txmsyncn is configured as an input, txmsyncn must pulse "high" for one period of txserclk during the first bit of an outbound ds1/e1 multi-frame. it is imperative that the txmsync input signal be synchronized with the txserclk input signal. if txmsyncn is configured as an output, the transmit section of the t1/e1 framer will output and pulse txmsync "high" for one period of txserclk during the first bit of an outbound ds1/e1 frame. ds1/e1 high-speed backplane modes* - (txinclkn as input only) in this mode, this pin must be used as the high-speed input clock pin (txinclkn) fo r the backplane inte rface to latch in high-speed or multiplexed data on the txsern pin. the fre - quency of txinclk is presented in the table below. n otes : 1. *high-speed backplane modes include (for t1/e1) 2.048mvip, 4.096mhz, 8.192mhz, 16.384mhz hmvip, h.100, bit-multip lexed modes, and (for t1 only) 12.352mhz bit-multiplexed mode. 2. in ds1 high-speed modes, the ds-0 data is mapped into an e1 frame by ignoring every fourth time slot (don?t care). 3. these 8 pins are internally pulled ?low? for each channel. transmit system side interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription o peration m ode f requency of t x inclk(mh z ) 2.048mvip non-multiplexed 2.048 4.096mhz non-multiplexed 4.096 8.192mhz non-multiplexed 8.192 12.352mhz bit-multiplexed (ds1 only) 12.352 16.384mhz bit-multiplexed 16.384 16.384 hmvip byte-multiplexed 16.384 16.384 h.100 byte-multiplexed 16.384 XRT86VX38 17 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 txsig0 txsig1 txsig2 txsig3 txsig4 txsig5 txsig6 txsig7 a10 b15 b18 g18 v16 w13 u10 u6 i/o 8 transmit time slot octet iden tifier output 0 (txchnn_0) / transmit serial signaling input (txsign): the exact function of these pi ns depends on whether or not the transmit framer enables the transmit fractional/signaling interface, as described below: if transmit fractional/signa ling interface is disabled - - no function if transmit fractional/signa ling interface is enabled - txsign: these pins can be used to input robbed-bit signaling data to be inserted within an outbound ds1 frame or to input channel associated signaling (cas) data within an outbound e1 frame, as described below. t1 mode: signaling data (a,b,c,d) of each channel must be provided on bit 4,5,6,7 of each ti me slot on the txsig pin if 16- code signaling is used. if 4-code signaling is selected, signal - ing data (a,b) of each channel must be provided on bit 4, 5 of each time slot on the txsig pin. if 2-code signaling is selected, signaling data (a) of each channel must be provided on bit 4 of each time slot on the txsig pin. e1 mode: signaling data in e1 mode can be provided on the txsign pins on a time-slot-basis as in t1 mode, or it can be provided on time slot 16 only via the txsign input pins. in the latter case, signaling data (a,b,c,d) of channel 1 and channel 17 must be inserted on the txsign pin during time slot 16 of frame 1, signaling data (a,b,c,d) of channel 2 and channel 18 must be inserted on the txsign pin during time slot 16 of frame 2...etc. the c as multiframe alignments bits (0000 bits) and the extra bits/alarm bit (xyxx) must be inserted on the txsign pin during time slot 16 of frame 0. n ote : transmit fractional interface can be enabled by programming to bit 4 - txfr1544/txfr2048 bit from register 0xn120 to ?1?. n ote : these 8 pins are internally pulled ?low? for each channel. transmit system side interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription XRT86VX38 18 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description receive system side interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription rxsync0/ rxneg0 rxsync1/ rxneg1 rxsync2/ rxneg2 rxsync3/ rxneg3 rxsync4/ rxneg4 rxsync5/ rxneg5 rxsync6/ rxneg6 rxsync7/ rxneg7 a8 c13 c15 e17 t17 u14 t10 t8 b9 a11 a13 c16 n13 n11 t9 r7 i/o 12 receive single frame sync pulse (rxsyncn): the exact function of these pins depends on the mode of operation selected, as described below. ds1/e1 base rate mode (1.544mhz/2.048mhz) - rxsyncn: these rxsyncn pins are used to indicate the single frame boundary within an inbound t1/e1 frame. in both ds1 or e1 mode, the single frame boundary repeats every 125 microseconds (8khz). in ds1/e1 base rate, rxsyncn can be configured as either input or output dependi ng on the slip buffer configu - ration as described below. when rxsyncn is configured as an input : users must provide a signal which must pulse "high" for one period of rxserclk and repeats every 125 ? s. the receive serial interface will output the first bit of an inbound ds1/e1 frame during the provided rxsync pulse. n ote : it is imperative that the rxsync input signal be synchronized with the rxserclk input signal. when rxsyncn is configured as an output: the receive t1/e1 framer will output a signal which pulses "high" for one period of rxserclk during the first bit of an inbound ds1/e1 frame. ds1/e1 high-speed backplane modes* - rxsyncn as input only: in this mode, rxsyncn must be an input regardless of the slip buffer configuration. in 2.048mvip/4.096/ 8.192mhz high-speed modes, rxsyncn pins must be pulsed ?high? for one period of rxserclk during the first bit of the inbound t1/e1 frame. in hmvip mode, rxsyncn must be pulsed ?high? for 4 clock cycles of the rxserclk signal in the position of the first two and the last two bits of a multiplexed frame. in h.100 mode, rxsyncn must be pulsed ?high? for 2 clock cycles of the rxserclk signal in the position of the first and the last bit of a multiplexed frame. ds1 or e1 framer bypass mode - rxnegn in this mode, rxsyncn is used as the receive negative digital output pin (rxneg) from the liu. n ote : *high-speed backplane modes include (for t1/ e1) 2.048mvip, 4.096mhz, 8.192mhz, 16.384mhz hmvip, h.100, bit-multiplexed modes, and (for t1 only) 12.352mhz bit- multiplexed mode. n ote : in ds1 high-speed modes, the ds-0 data is mapped into an e1 frame by ignoring every fourth time slot (don?t care). n ote : these 8 pins are internally pulled ?low? for each channel. XRT86VX38 19 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 rxcrcsync0 rxcrcsync1 rxcrcsync2 rxcrcsync3 rxcrcsync4 rxcrcsync5 rxcrcsync6 rxcrcsync7 d10 d12 a17 c19 v19 w16 v10 r7 a8 c10 c14 e12 r15 r13 r9 n7 o 12 receive multiframe sync pulse (rxcrcsyncn): the rxcrcsyncn pins are used to indicate the receive multi-frame boundary. these pins pulse "high" for one period of rxserclk when the first bit of an inbound ds1/e1 multi-frame is being output on the rxcrcsyncn pin. ? in ds1 esf mode, rxcrcsyncn repeats every 3ms ? in ds1 sf mode, rxcrcsyncn repeats every 1.5ms ? in e1 mode, rxcrcsyncn repeats every 2ms. rxcasync0 rxcasync1 rxcasync2 rxcasync3 rxcasync4 rxcasync5 rxcasync6 rxcasync7 e10 c14 a16 d19 u17 v15 w10 t9 a9 d11 d13 e13 r14 r12 n9 m8 o 12 receive cas multiframe sync pulse (rxcasyncn): - e1 mode only the rxcasyncn pins are used to indicate the e1 cas multif-frame boundary. these pins pulse "high" for one period of rxserclk when the first bit of an e1 cas multi-frame is being output on the rxcasyncn pin. receive system side interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription XRT86VX38 20 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description rxserclk0/ rxlineclk0 rxserclk1/ rxlineclk1 rxserclk2/ rxlineclk2 rxserclk3/ rxlineclk3 rxserclk4/ rxlineclk4 rxserclk5/ rxlineclk5 rxserclk6/ rxlineclk6 rxserclk7/ rxlineclk7 d9 a11 b16 f16 r17 t15 t12 u7 b8 a10 c13 d15 p14 t12 m10 r6 i/o 12 receive serial clock signal (rxserclkn) / receive line clock (rxlineclkn): the exact function of these pins depends on the mode of operation selected, as described below. in base-rate mode (1.5 44mhz/2.048mhz) - rxser - clkn: these pins are used as the receive serial clock on the system side interface which ca n be configured as either input or output. the receive serial interface outputs data on rxsern on the rising edge of rxserclkn. when rxserclkn is configured as input: these pins will be inputs if the slip buffer on the receive path is enabled. system side equipment must provide a 1.544mhz clock rate to this input pin for t1 mode of oper - ation, and 2.048mhz clock rate in e1 mode. when rxserclkn is configured as output: these pins will be outputs if slip buffer is bypassed. the receive framer will output a 1.544mhz clock rate in t1 mode of operation, and a 2.048mhz clock rate in e1 mode. ds1/e1 high-speed backplane modes* - (rxserclk as input only) in this mode, this pin must be used as the high-speed input clock for the backplane interface to output high- speed or multiplexed data on the rxsern pin. the fre - quency of rxserclk is presented in the table below. n otes : 1. *high-speed backplane modes include (for t1/ e1) 2.048mvip, 4.096mhz, 8.192mhz, 16.384mhz hmvip, h.100, bit-multiplexed modes, and (for t1 only) 12.352mhz bit- multiplexed mode. 2. for ds1 high-speed modes, the ds-0 data is mapped into an e1 frame by ignoring every fourth time slot (don?t care). receive system side interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription o peration m ode f requency of r x serclk(mh z ) 2.048mvip non-multiplexed 2.048 4.096mhz non-multiplexed 4.096 8.192mhz non-multiplexed 8.192 12.352mhz bit-multiplexed (ds1 only) 12.352 16.384mhz bit-multiplexed 16.384 16.384 hmvip byte-multiplexed 16.384 16.384 h.100 byte-multiplexed 16.384 XRT86VX38 21 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 rxserclk0/ rxlineclk0 rxserclk1/ rxlineclk1 rxserclk2/ rxlineclk2 rxserclk3/ rxlineclk3 rxserclk4/ rxlineclk4 rxserclk5/ rxlineclk5 rxserclk6/ rxlineclk6 rxserclk7/ rxlineclk7 d9 a11 b16 f16 r17 t15 t12 u7 b8 a10 c13 d15 p14 t12 m10 r6 i/o 12 (continued) ds1 or e1 framer bypass mode - rxlineclkn in this mode, rxserclkn is used as the receive line clock output pin (rxlineclk) from the liu. n ote : these 8 pins are internally pulled ?high? for each channel. rxser0/ rxpos0 rxser1/ rxpos1 rxser2/ rxpos2 rxser3/ rxpos3 rxser4/ rxpos4 rxser5/ rxpos5 rxser6/ rxpos6 rxser7/ rxpos7 d8 c12 b17 b19 v18 v14 w12 v8 b7 b11 b14 b16 p15 p11 t10 p8 o 12 receive serial data output (rxsern): the exact function of these pins depends on the mode of operation selected, as described below. ds1/e1 mode - rxsern these pins function as the receive serial data output on the system side interface, whic h are updated on the rising edge of the rxserclkn pin. all the framing alignment bits, facility data link bits, crc bits, and signaling informa - tion will also be extracted to this output pin. ds1 or e1 high-speed multiplexed mode* - rxsern in this mode, these pins are used as the high-speed multi - plexed data output pin on the system side. high-speed multiplexed data of channels 0-3 will output on rxser0 and high-speed multiplexed data of channels 4-7 will out - put on rxser4 in a byte or bit-interleaved way. the framer outputs the multiplexed data on rxser0 and rxser4 using the high-speed input clock (rxserclkn). ds1 or e1 framer bypass mode in this mode, rxsern is used as the positive digital out - put pin (rxposn) from the liu. n ote : *high-speed multiplexed modes include (for t1/ e1) 16.384mhz hmvip, h.100, bit-multiplexed modes, and (for t1 only) 12.352mhz bit- multiplexed mode. n ote : in ds1 high-speed modes, the ds-0 data is mapped into an e1 frame by ignoring every fourth time slot (don?t care). receive system side interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription XRT86VX38 22 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description rxsig0 rxsig1 rxsig2 rxsig3 rxsig4 rxsig5 rxsig6 rxsig7 a7 b12 c16 d18 u18 w14 v12 u9 o 8 receive serial signal ing output (rxsign): the exact function of these pins depends on whether or not the receive framer enables the receive fractional/sig - naling interface, as described below: if receive fractional/signaling interface is disabled : -no function if receive fractional/signaling interface is enabled - rxsign: these pins can be used to output robbed-bit signaling data within an inbound ds1 frame or to output channel associated signaling (cas) data within an inbound e1 frame, as described below. t1 mode: signaling data (a,b,c,d) of each channel will be output on bit 4,5,6,7 of each time slot on the rxsig pin if 16-code signaling is used. if 4-code signaling is selected, signaling data (a,b) of each channel will be out - put on bit 4, 5 of each time slot on the rxsig pin. if 2- code signaling is selected, signaling data (a) of each channel will be output on bit 4 of each time slot on the rxsig pin. e1 mode: signaling data in e1 mode will be output on the rxsign pins on a time-slot-basis as in t1 mode, or it can be output on time slot 16 only via the rxsign output pins. in the latter case, signaling data (a,b,c,d) of channel 1 and channel 17 will be output on the rxsign pin during time slot 16 of frame 1, signaling data (a,b,c,d) of chan - nel 2 and channel 18 will be output on the rxsign pin during time slot 16 of frame 2...etc. the cas multiframe alignments bits (0000 bits) and the extra bits/alarm bit (xyxx) will be output on the rxsign pin during time slot 16 of frame 0. n ote : receive fractional/signaling interface can be enabled by programming to bit 4 - rxfr1544/ rxfr2048 bit from register 0xn122 to ?1?. rxsclk0 rxsclk1 rxsclk2 rxsclk3 rxsclk4 rxsclk5 rxsclk6 rxsclk7 c11 e14 a18 f17 w18 t14 u11 u8 b10 d12 a15 f12 t15 t11 p9 m7 o 8 receive recovered line clock output (rxsclkn): the exact function of these pins depends on whether or not the receive framer enables the receive fractional/sig - naling interface, as described below: if receive fractional/signaling interface is disabled - -no function if receive fractional/signaling interface is enabled - receive recovered line clock output (rxsclkn): these pins output the recovered t1/e1 line clock (1.544mhz in t1 mode and 2.048mhz in e1 mode) for each channel. n ote : receive fractional/signaling interface can be enabled by programming to bit 4 - rxfr1544/ rxfr2048 bit from register 0xn122 to ?1?. receive system side interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription XRT86VX38 23 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 receive line interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription rtip0 rtip1 rtip2 rtip3 rtip4 rtip5 rtip6 rtip7 c1 e1 h1 k1 m1 p1 t1 w2 b1 d1 f1 h1 k1 m1 p1 t2 i - receive positive analog input (rtipn): rtip is the positive different ial input from the line inter - face. this input pin, along with the rring input pin, func - tions as the ?receive ds1/e1 line signal? input for the XRT86VX38 device. the user is expected to connect this signal and the rring input signal to a 1:1 transformer for proper opera - tion. the center tap of the receive transformer should have a bypass capacitor of 0.1 ? f to ground (chip side) to improve long haul application receive capabilities. rring0 rring1 rring2 rring3 rring4 rring5 rring6 rring7 d1 f1 j1 l1 n1 r1 u1 w3 c1 e1 g1 j1 l1 n1 r1 t3 i - receive negative analog input (rringn): rring is the negative differenti al input from the line inter - face. this input pin, along with the rtip input pin, func - tions as the ?receive ds1/e1 line signal? input for the XRT86VX38 device. the user is expected to connect this signal and the rtip input signal to a 1:1 transformer for proper operation. the center tap of the receive transformer should have a bypass capacitor of 0.1 ? f to ground (chip side) to improve long haul application receive capabilities. rxlos0 rxlos1 rxlos2 rxlos3 rxlos4 rxlos5 rxlos6 rxlos7 b8 b13 d15 e18 u19 u15 v11 v7 a7 c11 f11 d16 p16 p12 r10 p7 o 4 receive loss of signal output indicator (rlosn): the XRT86VX38 device will assert this output pin (i.e., toggle it ?high?) anytime (and for the duration that) the receive ds1/e1 framer or liu block declares the los defect condition. conversely, the XRT86VX38 wil l "tri-state" this pin any - time (and for the duration that) the receive ds1/e1 framer or liu block is not declaring the los defect con - dition. n ote : since the XRT86VX38 tri-states this output pin (anytime the channel is not declaring the los defect condition), the user must connect a "pull- down" resistor (ranging from 1k to 10k) to each rxlos output pin, to pull this output pin to the logic "low" condition, whenever the channel is not declaring the los defect condition. this output pin will toggle ?hi gh? (declare los) if the receive framer or the receive liu block associated with channel n determines that an rlos condition occurs. in other words, this pin is or-ed with the liu rlos and the framer rlos bit. if either the liu rlos or the framer rlos bit associated with channel n pulses high, the cor - responding rlos pin of that particular channel will be set to ?high?. XRT86VX38 24 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description rxtsel b5 a5 i - receive termination control (rxtsel): upon power up, the receivers are in "high" impedance. switching to internal termination can be selected through the microprocessor interface by programming the appro - priate channel register. however, to switch control to the hardware pin, rxtcntl must be programmed to "1" in the appropriate global register (0x0fe2). once control has been granted to the hardware pin, it must be pulled "high" to switch to internal termination. n ote : internally pulled "low" with a 50k ?? resistor. transmit line interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype d escription ttip0 ttip1 ttip2 ttip3 ttip4 ttip5 ttip6 ttip7 d3 f3 h4 k4 l3 n3 r5 t3 c3 e3 g3 h3 j3 l3 m3 p3 o transmit positive analog output (ttipn): ttip is the positive differential output to the line interface. this out - put pin, along with the correspondin g tring output pin, function as the transmit ds1/e1 output signal drivers for the XRT86VX38 device. the user is expected to connect this signal and the corresponding tring output signal to a 1:2 step up transformer for proper opera - tion. this output pin will be tri-stated w henever the user sets the ?txon? input pin or register bit (0xnf02, bit 3) to ?0?. n ote : this pin should have a series line capacitor of 0.68 ? f for dc blocking purposes. tring0 tring1 tring2 tring3 tring4 tring5 tring6 tring7 e3 f4 h3 k3 l4 n4 r4 u3 d3 e4 g4 h4 j4 l4 m4 p4 o transmit negative anal og output (tringn): tring is the negative differential output to the line interface. this output pin, along with the correspondi ng ttip output pin, function as the transmit ds1/e1 output signal drivers for the XRT86VX38 device. the user is expected to connect this signal and the corresponding tring output signal to a 1:2 step up transformer for proper opera - tion. n ote : this output pin will be tri-stated whenever the user sets the ?txon? input pin or register bit (0xnf02, bit 3) to ?0?. receive line interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription rxtsel (pin) rx termination external internal 0 1 note: rxtcntl (bit) must be set to "1" XRT86VX38 25 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 txon w4 t4 i transmitter on this input pin permits the user to either enable or disable the trans - mit output driver within the transmit ds1/e1 li u block. if the txon pin is pulled ?low?, all 8 channels are tri-stated. when this pin is pulled ?high?, turning on or off the transmitters will be determined by the appropriate channel registers (address 0x0fn2, bit 3) low = disables the transmit output driver within the transmit ds1/ e1 liu block. in this setting, the ttip and tring output pins of all 8 channels will be tri-stated. high = enables the transmit output driver within the transmit ds1/ e1 liu block. in this setting, the corresponding ttip and tring out - put pins will be enabled or disabled by programming the appropriate channel register. (address 0x0fn2, bit 3) n ote : whenever the transmitters are turned off, the ttip and tring output pins will be tri-stated. timing interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription mclkin c8 e6 i - master clock input: this pin is used to provide the timing reference for the inter - nal master clock of the device. the frequency of this clock is programmable from 8khz to 16.384mhz in register 0x0fe9. e1oscclk v5 r5 o 8 framer e1 output clock reference this output pin is defaulted to 2.048mhz, but can be pro - grammed to 65.536mhz in register 0x011e. t1oscclk w5 t5 o 8 framer t1 output clock reference this output pin is defaulted to 1.544mhz, but can be pro - grammed to output 49.408mhz in register 0x011e. 8kextosc t5 l6 i - external oscillator select for normal operation, this pin should not be used, or pulled ?low?. this pin is internally pulled ?low? with a 50k ? resistor. analog e5 b4 o factory test mode pin n ote : for internal use only transmit line interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype d escription XRT86VX38 26 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description jtag interface the XRT86VX38 device?s jtag featur es comply with the ieee 1149.1 standa rd. please refer to the industry specification for additional information on boundary scan operations. s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription tck c10 d8 i - test clock: boundary scan test clock input: the tclk signal is the clock for the tap controller, and it generates the boundary scan data register clocking. the data on tms and tdi is loaded on the positive edge of tck. data is observed at tdo on the falling edge of tck. tms b7 a6 i - test mode select: boundary scan test mode select input. the tms signal controls the transitions of the tap con - troller in conjunction with the rising edge of the test clock (tck). n ote : for normal operation this pin must be pulled ?high?. tdi a5 c8 i - test data in: boundary scan test data input the tdi signal is the serial test data input. n ote : this pin is internally pulled ?high?. tdo d7 b6 o 8 test data out: boundary scan test data output the tdo signal is the serial test data output. trst c9 d7 i - test reset input: the trst signal (active low) asynchronously resets the tap controller to the test-logic-reset state. n ote : this pin is internally pulled ?high? atest c7 c7 i - factory test mode pin n ote : this pin is internally pulled ?low?, and should be pulled ?low? for normal operation. microprocessor interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription data0 data1 data2 data3 data4 data5 data6 data7 n16 p19 k16 l18 j19 h18 h16 g15 m14 l12 k12 j12 h13 g14 g12 g13 i/o 8 bidirectional microprocessor data bus these pins are used to drive and receive data over the bi- directional data bus, whenever the microprocessor per - forms read or write operations with the microprocessor interface of the XRT86VX38 device. when dma interface is enabled, these 8-bit bidirectional data bus is also used by the t1/e1 framer or the external dma controller for storing and retrieving information. XRT86VX38 27 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 req0 t19 n16 o 8 dma cycle request output?d ma controller 0 (write) : these output pins are used to indicate that dma transfers (write) are requested by the t1/e1 framer. on the transmit side (i.e., to transmit data from external dma controller to hdlc buffers within the XRT86VX38), dma transfers are only requested when the transmit buffer status bits indicate that there is space for a complete mes - sage or cell. the dma write cycle starts by t1/e1 framer asserting the dma request ( req0) ?low?, then the ex ternal dma control - ler should drive the dma acknowledge ( ack0) ?low? to indi - cate that it is ready to start the transfer. the external dma controller should place new data on the microprocessor data bus each time the write signal is strobed low if the wr is configured as a write strobe. if wr is configured as a direction signal, then the external dma controller would place new data on the microprocessor data bus each time the read signal (rd) is strobed low. the framer asserts this output pin (toggles it "low") when at least one of the transmit hdlc buffers are empty and can receive one more hdlc message. the framer negates this output pin (toggles it ?high?) when the hdlc buffer can no longer receive another hdlc mes - sage. req1 r16 r16 o 8 dma cycle request output?d ma controller 1 (read): these output pins are used to indicate that dma transfers (read) are requested by the t1/e1 framer. on the receive side (i.e., to transmit data from hdlc buff - ers within the XRT86VX38 to external dma controller), dma transfers are only requested when the receive buffer contains a complete message or cell. the dma read cycle starts by t1/e1 framer asserting the dma request ( req1) ?low?, then the ex ternal dma control - ler should drive the dma acknowledge ( ack1) ?low? to indi - cate that it is ready to rece ive the data. the t1/e1 framer should place new data on the microprocessor data bus each time the read signal is strobed low if the rd is con - figured as a read strobe. if rd is configured as a direction signal, then the t1/e1 framer would place new data on the microprocessor data bus each time the write signal (wr) is strobed low. the framer asserts this output pin (toggles it "low") when one of the receive hdlc buffer contains a complete hdlc message that needs to be read by the c/p. the framer negates this output pin (toggles it ?high?) when the receive hdlc buffers are depleted. microprocessor interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription XRT86VX38 28 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description int j18 h15 o 8 interrupt request output: this active-low output signal will be asserted when the XRT86VX38 device is requesting interrupt service from the microprocessor. this output pin should typically be con - nected to the ?interrupt request? input of the microproces - sor. the framer will assert this active "low" output (toggles it "low"), to the local p, anytime it requires interrupt service. pclk p18 m16 i - microprocessor clock input: this clock input signal is only used if the microprocessor interface has been configured to operate in the synchro - nous modes (e.g., power pc 403 mode). if the micropro - cessor interface is configured to operate in this mode, then it will use this clock signal to do the following. 1. to s a m p l e t h e cs , wr /r/ w , a[14:0], d[7:0], rd / ds and dben input pins, and 2. to update the state of the d[7:0] and the rdy/ dtack output signals. n otes : 1. the microprocessor interface can work with pclk frequencies ranging up to 33mhz. 2. this pin is inactive if the user has configured the microprocessor interface to operate in either the intel-asynchronous or the motorola- asynchronous modes. in this case, the user should tie this pin to gnd. when dma interface is enabled, the pclk input pin is also used by the t1/e1 framer to latch in or latch out receive or output data respectively. ptype0 ptype1 ptype2 p17 n18 k19 m13 m12 h12 i - microprocessor type input: these input pins permit the user to specify which type of microprocessor/microcontroller to be interfaced to the XRT86VX38 device. the following table presents the three different microprocessor types that the XRT86VX38 sup - ports. n ote : these pins are internally pulled ?low? with a 50k ? resistor. microprocessor interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription 0 1 1 ? ptype0 0 0 0 0 0 1 ? ptype1 ? ptype2 68hc11, 8051, 80c188 motorola 68k ibm power pc 403 microprocessor type XRT86VX38 29 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 rdy / dtack m16 l16 o 12 ready/data transfer acknowledge output: the exact behavior of this pin depends upon the type of microprocessor/microcontroller the XRT86VX38 has been configured to operate in, as defined by the ptype[2:0] pins. intel asynchronous mode - rdy - ready output tis output pin will function as the ?active-low? ready out - put. during a read or write cycle, the microprocessor inter - face block will toggle this output pin to the logic low level, only when the microprocessor interface is ready to com - plete or terminate the current read or write cycle. once the microprocessor has determined that this input pin has toggled to the logic ?low? level, then it is now safe for it to move on and execute the next read or write cycle. if (during a read or writ e cycle) the microprocessor interface block is holding this output pin at a logic ?high? level, then the microprocessor is expected to extend this read or write cycle, until it detects this output pin being toggled to the logic low level. motorola asynch ronous mode - dtack - data transfer acknowledge output tis output pin will function as the ?active-low? dtack out - put. during a read or write cycle, the microprocessor inter - face block will toggle this output pin to the logic low level, only when the microprocessor interface is ready to com - plete or terminate the current read or write cycle. once the microprocessor has determined that this input pin has toggled to the logic ?low? level, then it is now safe for it to move on and execute the next read or write cycle. if (during a read or writ e cycle) the microprocessor interface block is holding this output pin at a logic ?high? level, then the microprocessor is expected to extend this read or write cycle, until it detects this output pin being toggled to the logic low level. microprocessor interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription XRT86VX38 30 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description rdy / dtack m16 l16 o 12 (con?t) power pc 403 mode - rdy ready output: this output pin will function as the ?active-high? ready output. during a read or write cycle, the microprocessor inter - face block will toggle this output pin to the logic high level, only when the microprocessor interface is ready to com - plete or terminate the current read or write cycle. once the microprocessor has sampled this signal being at the logic ?high? level upon the rising edge of pclk, then it is now safe for it to move on and execute the next read or write cycle. if (during a read or writ e cycle) the microprocessor interface block is holding this output pin at a logic ?low? level, then the microprocessor is expected to extend this read or write cycle, until it samples this output pin being at the logic low level. n ote : the microprocessor interface will update the state of this output pin upon the rising edge of pclk. addr0 addr1 addr2 addr3 addr4 addr5 addr6 addr7 addr8 addr9 addr10 addr11 addr12 addr13 addr14 n19 m17 m18 m15 l16 m19 l17 l19 k15 j16 k18 j15 h15 h19 h17 l13 l14 k15 l11 k13 k16 k14 j15 j14 j13 h14 h16 g16 f16 g11 i - microprocessor interface address bus input these pins permit the microprocessor to identify on-chip registers and buffer/memory locations within the XRT86VX38 device whenever it performs read and write operations with the XRT86VX38 device. n ote : these pins are internally pulled ?low? with a 50k ? resistor, except addr[8:14]. microprocessor interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription XRT86VX38 31 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 ale / as k17 j16 i - address latch enable input address strobe the exact behavior of this pin depends upon the type of microprocessor/microcontroller the XRT86VX38 has been configured to operate in, as defined by the ptype[2:0] pins. intel-asynchronous mode - ale this active-high input pin is used to latch the address (present at the microprocessor interface address bus pins (a[14:0]) into the XRT86VX38 microprocessor interface block and to i ndicate the start of a read or write cycle. pulling this input pin ?high? enables the input bus drivers for the address bus input pins (a[14:0]). the contents of the address bus will be latched into the XRT86VX38 micropro - cessor interface circuitry, upon the falling edge of this input signal. motorola-asynchrono us (68k) mode - as this active-low input pin is used to latch the data residing on the address bus, a[14:0] into the microprocessor inter - face circuitry of t he XRT86VX38 device. pulling this input pin ?low? enables the input bus drivers for the address bus input pins. the contents of the address bus will be latched into the microprocessor interface cir - cuitry, upon the rising edge of this signal. power pc 403 mode - no function -tie to gnd: this input pin has no role nor function and should be tied to gnd. cs g19 f14 i - microprocessor interface?chip select input: the user must assert this active low signal in order to select the microprocessor interface for read and write operations between the microprocessor and the XRT86VX38 on-chip registers and buffer/memory loca - tions. microprocessor interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription XRT86VX38 32 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description rd / ds / we n17 l15 i - microprocessor interface?read strobe input: the exact behavior of this pin depends upon the type of microprocessor/microcontroller the framer has been con - figured to operate in, as de fined by the ptype[2:0] pins. intel-asynchronous mode - rd - read strobe input: this input pin will function as the rd (active low read strobe) input signal from the microprocessor. once this active-low signal is asserted, then the XRT86VX38 device will place the contents of the addressed register (or buffer location) on the microprocessor interface bi-directional data bus (d[7:0]). when this signal is negated, then the data bus will be tri- stated. motorola-asynchrono us (68k) mode - ds - data strobe: this input pin will function as the ds (data strobe) input signal. power pc 403 mode - we - write enable input: this input pin will function as the we (write enable) input pin. anytime the microprocessor inte rface samples this active- low input signal (along with cs and wr /r/ w ) also being asserted (at a logic low level) upon the rising edge of pclk, then the microprocessor interface will (upon the very same rising edge of pclk) latch the contents on the bi-directional data bus (d[7:0]) into the ?target? on-chip register or buffer location within the XRT86VX38 device. wr / r/ w g17 f13 i - microprocessor interface?write strobe input the exact behavior of this pin depends upon the type of microprocessor/microcontroller the XRT86VX38 has been configured to operate in, as defined by the ptype[2:0] pins. intel-asynchronous mode - wr - write strobe input: this input pin functions as the wr (active low write strobe) input signal from the microprocessor. once this active-low signal is asserted, then the input buffers (associ - ated with the bi-directional data bus pin, d[7:0]) will be enabled. the microprocessor interface w ill latch the contents on the bi-directional data bus (into the ?target? register or address location, within the XRT86VX38) upon the rising edge of this input pin. motorola-asynchro nous mode - r/ w - read/write operation identification input pin: this pin is functionally equivalent to the ?r/ w ? input pin. in the motorola mode, a ?read? operation occurs if this pin is held at a logic ?1?, coincident to a falling edge of the rd/ ds (data strobe) input pin. similarly a write operation occurs if this pin is at a logic ?0?, coincident to a falling edge of the rd/ ds (data strobe) input pin. microprocessor interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription XRT86VX38 33 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 wr / r/ w g17 f13 i - (con?t) power pc 403 mode - r/ w - read/write operation iden - tification input: this input pin will function as the ?read/write operation identification input? pin. anytime the microprocessor in terface samples this input signal at a logic "high" (while also sampling the cs input pin ?low?) upon the rising edge of pclk, then the micro - processor interface will (upon the very same rising edge of pclk) latch the contents of t he address bus (a[14:0]) into the microprocessor interface circui try, in preparation for this forthcoming read operation. at some point (later in this read operation) the microprocessor will also assert the dben/oe input pin, and the microprocessor interface will then place the contents of the ?target? register (or address location within the XRT86VX38 device) upon the bi-direc - tional data bus pins (d[7:0]), where it can be read by the microprocessor. anytime the microprocessor in terface samples this input signal at a logic "low" (while also sampling the cs input pin a logic ?low?) upon the rising edge of pclk, then the microprocessor interface will (upon the very same rising edge of pclk) latch the contents of the address bus (a[14:0]) into the microprocessor interface circuitry, in preparation for the forthcoming write operation. at some point (later in this write operation) the microprocessor will also assert the rd/ds/we input pin, and the micropro - cessor interface will then latch the contents of the bi-direc - tional data bus (d[7:0]) into the contents of the ?target? register or buffer location (within the XRT86VX38). microprocessor interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription XRT86VX38 34 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description ack0 ack1 t18 r19 n15 m15 i - dma cycle acknowledge in put?dma controller 0 (write): the external dma controller will assert this input pin ?low? when the following two conditions are met: 1. after the dma controller, within the framer has asserted (toggled ?low?), the req_0 output signal. 2. when the external dma controller is ready to transfer data from external memory to the selected transmit hdlc buffer. at this point, the dma tran sfer between the external mem - ory and the selected transmit hdlc buffer may begin. after completion of the dma cycle, the external dma con - troller will negate this input pin after the dma controller within the framer has negated the req_0 output pin. the external dma controller must do this in order to acknowl - edge the end of the dma cycle. dma cycle acknowledge in put?dma controller 1 (read): the external dma controller asserts this input pin ?low? when the following two conditions are met: 1. after the dma controller, within the framer has asserted (toggled "low"), the req_1 output signal. 2. when the external dma controller is ready to transfer data from the selected receive hdlc buffer to external memory. at this point, the dma tr ansfer between the selected receive hdlc buffer and the external memory may begin. after completion of the dma cycle, the external dma con - troller will negate this input pin after the dma controller within the framer has negated the req_1 output pin. the external dma controller will do this in order to acknowl - edge the end of the dma cycle. n ote : this pin is internally pulled ?high? with a 50k ? resistor. reset v4 r4 i - hardware reset input reset is an active low input. if this pin is pulled ?low? for more than 10 ? s, the device will be reset. when this occurs, all output will be ?tri-stated?, and all internal registers will be reset to their default values. microprocessor interface s ignal n ame 329 p kg b all # 256 p kg b all # t ype o utput d rive ( m a) d escription XRT86VX38 35 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 power supply pins (3.3v) s ignal n ame 329 p kg b all # 256 p kg b all # t ype d escription vdd a1 a12 a19 b6 b9 e16 f5 j17 p16 r11 r13 r15 r18 t7 u4 v1 w11 w15 a16 e8 e11 g15 m6 m9 n14 t16 pwr framer block power supply (i/o) rvdd c2 e2 g1 j2 l2 n2 p4 u2 b2 d2 f2 h2 k2 m2 p2 t1 pwr receiver analog power supply for liu section tvdd d4 g4 j4 k5 m4 n5 r3 t4 d4 f4 f5 h5 k4 k5 m5 n4 pwr transmitter analog power supply for liu section XRT86VX38 36 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description power supply pins (1.8v) s ignal n ame 329 p kg b all # 256 p kg b all # t ype d escription vdd18 d13 e6 e8 e9 e11 e12 e13 e15 f15 g5 g7 g9 g11 g13 j5 j7 j13 l7 l13 l15 m5 n7 n9 n11 n13 p15 r9 r10 r12 r14 t6 f8 f9 f10 g6 h6 h11 j6 j11 k6 k11 l7 l8 l9 l10 pwr framer block power supply dvdd18 b4 c6 pwr digital power supply for liu section avdd18 d6 c5 pwr analog power supply for liu section vddpll18 a2 b2 b3 c4 a3 a4 b3 d5 pwr analog power supply for pll XRT86VX38 37 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 ground pins s ignal n ame 329 p kg b all # 256 p kg b all # t ype d escription vss a3, a6 a15, c5 e7, f2 g8, g10 g12, h5 h7, h8 h9, h10 h11, h12 h13, j8 j9, j10 j11, j12 k7, k8 k9, k10 k11, k12 k13, l8 l9, l10 l11, l12 m7, m8 m9, m10 m11, m12 m13, n8 n10, n12 n15, p2 r6, u12 w1, w19 e7 e9 f6 f7 g7 g8 g9 g10 h7 h8 h9 h10 j7 j8 j9 j10 k7 k8 k9 k10 gnd framer block ground dgnd a4 d6 gnd digital ground for liu section agnd c6 b5 gnd analog ground for liu section rgnd d2 g2 h2 k2 m2 r2 t2 v3 c2 e2 g2 j2 l2 n2 r2 r3 gnd receiver analog ground for liu section tgnd e4 g3 j3 l5 m3 p3 p5 v2 e5 f3 g5 j5 k3 l5 n3 n5 gnd transmitter analog ground for liu section XRT86VX38 38 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description gndpll b1 c3 d5 a1 a2 c4 gnd analog ground for pll no connect pins s ignal n ame 329 p kg b all # 256 p kg b all # t ype d escription nc f6 f7 f8 f9 f10 f11 f12 f13 f14 g6 g14 h6 h14 j6 j14 k6 k14 l6 l14 m6 m14 n6 n14 p6 p7 p8 p9 p10 p11 p12 p13 p14 nc no connection ground pins s ignal n ame 329 p kg b all # 256 p kg b all # t ype d escription XRT86VX38 39 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 electrical characteristics absolute maximums power supply..................................................................... vdd io .. ................................................ - 0.5v to +3.465v vdd core............................................... - 0.5v to +1.890v power rating fpbga pa ckage.................. 2.4 storage temperature ...............................-65c to 150c input logic signal voltage (any pin) .........-0.5v to + 5.5v operating temperature range.................-40c to 85c esd protection (hbm)...........................................>2000v supply voltage ...................... gnd-0.5v to +vdd + 0.5v input current (any pin) ...................................... + 100ma dc electrical characteristics test conditions: ta = 25c, vdd io = 3.3v + 5% , vdd core = 1.8v + 5% unless otherwise specified s ymbol p arameter m in . t yp . m ax . u nits c onditions i ll data bus tri-state bus leakage current -10 +10 a v il input low voltage 0.8 v v ih input high voltage 2.0 vdd v v ol output low voltage 0.0 0.4 v i ol = -1.6ma voh output high voltage 2.4 vdd v i oh = 40a i oc open drain output leakage current a i ih input high voltage current -10 10 a v ih = vdd i il input low voltage current -10 10 a v il = gnd XRT86VX38 power consumption test conditions: ta = 25c, vdd io = 3.3v + 5% , vdd core = 1.8v + 5%, internal termination, unless otherwise specified mode i mpedance m in . t yp . m ax . u nits c onditions t1 100 ? 2.02 1.54 w all ones pattern prbs pattern e1 75 ? 1.95 1.57 w all ones pattern prbs pattern e1 120 ? 1.77 1.44 w all ones pattern prbs pattern XRT86VX38 40 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description t able 4: e1 r eceiver e lectrical c haracteristics vdd io = 3.3v + 5% , vdd core = 1.8v + 5% , t a = -40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions receiver loss of signal: number of consecutive zeros before rlos is set input signal level at rlos rlos de-asserted 15 12.5 32 20 db % ones cable attenuation @1024khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 11 db with nominal pulse amplitude of 3.0v for 120 ? and 2.37v for 75 ? applica - tion. receiver sensitivity (long haul with cable loss) 0 43 db with nominal pulse amplitude of 3.0v for 120 ? and 2.37v for 75 ? applica - tion. input impedance 15 k ? input jitter tolerance: 1 hz 10khz-100khz 37 0.3 uipp uipp itu g.823 recovered clock jitter transfer corner frequency peaking amplitude - 20 0.5 khz db itu g.736 jitter attenuator corner fre - quency (-3db curve) (jabw=0) (jabw=1) - 10 1.5 - hz hz itu g.736 return loss: 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz 12 8 8 - - db db db itu-g.703 XRT86VX38 41 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 t able 5: t1 r eceiver e lectrical c haracteristics vdd io = 3.3v + 5% , vdd core = 1.8v + 5%, t a =-40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions receiver loss of signal: number of consecutive zeros before rlos is set input signal level at rlos rlos clear 15 12.5 175 20 - - - db % ones cable attenuation @772khz itu-g.775, etsi 300 233 receiver sensitivity (short haul with cable loss) 12 - db with nominal pulse amplitude of 3.0v for 100 ? termination receiver sensitivity (long haul with cable loss) normal extended 0 0 - 36 45 db db with nominal pulse amplitude of 3.0v for 100 ? termination input impedance 15 - k ? jitter tolerance: 1hz 10khz - 100khz 138 0.4 - - - - uipp at&t pub 62411 recovered clock jitter transfer corner frequency peaking amplitude - - 10 - 0.1 khz db tr-tsy-000499 jitter attenuator corner frequency (-3db curve) - 6 hz at&t pub 62411 return loss: 51khz - 102khz 102khz - 2048khz 2048khz - 3072khz - - - 14 20 16 - - - db db db t able 6: e1 t ransmitter e lectrical c haracteristics vdd io = 3.3v + 5% , vdd core = 1.8v + 5%, t a =-40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions ami output pulse amplitude: 75 ? application 120 ? application 2.13 2.70 2.37 3.00 2.60 3.30 v v 1:2 transformer output pulse width 224 244 264 ns output pulse width ratio 0.95 - 1.05 - itu-g.703 output pulse amplitude ratio 0.95 - 1.05 - itu-g.703 XRT86VX38 42 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description jitter added by the transmitter output - 0.025 0.05 uipp broad band with jitter free tclk applied to the input. output return loss: 51khz -102khz 102khz-2048khz 2048khz-3072khz 15 9 8 - - - - - - db db db etsi 300 166 t able 7: e1 t ransmit r eturn l oss r equirement f requency r eturn l oss ets 300166 51-102khz 6db 102-2048khz 8db 2048-3072khz 8db t able 8: t1 t ransmitter e lectrical c haracteristics vdd io = 3.3v + 5% , vdd core = 1.8v + 5% , t a =-40 to 85c, unless otherwise specified p arameter m in . t yp . m ax . u nit t est c onditions ami output pulse amplitude: 2.4 3.0 3.60 v 1:2 transformer measured at dsx-1. output pulse width 338 350 362 ns ansi t1.102 output pulse width imbalance - - 20 - ansi t1.102 output pulse amplitude imbalance - - + 200 mv ansi t1.102 jitter added by the transmitter output - 0.025 0.05 uipp broad band with jitter free tclk applied to the input. output return loss: 51khz -102khz 102khz-2048khz 2048khz-3072khz - - - 17 12 10 - - - db db db t able 6: e1 t ransmitter e lectrical c haracteristics vdd io = 3.3v + 5% , vdd core = 1.8v + 5%, t a =-40 to 85c, unless otherwise specified p arameter m in .t yp .m ax .u nit t est c onditions XRT86VX38 43 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 f igure 2. itu g.703 p ulse t emplate t able 9: t ransmit p ulse m ask s pecification test load impedance 75 ? resistive (coax) 120 ? resistive (twisted pair) nominal peak voltage of a mark 2.37v 3.0v peak voltage of a space (no mark) 0 + 0.237v 0 + 0.3v nominal pulse width 244ns 244ns ratio of positive and negative pulses imbalance 0.95 to 1.05 0.95 to 1.05 10% 10% 10% 10% 10% 10% 269 ns (244 + 25) 194 ns (244?50) 244 ns 219 ns (244 ? 25) 488 ns (244 + 244) 0% 50% 20% v = 100% nominal pulse note ? v corresponds to the nominal peak value. 20% 20% XRT86VX38 44 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description f igure 3. itu g.703 s ection 13 s ynchronous i nterface p ulse t emplate t able 10: e1 s ynchronous i nterface t ransmit p ulse m ask s pecification test load impedance 75 ? resistive (coax) 120 ? resistive (twisted pair) maximum peak voltage of a mark 1.5v 1.9v minimum peak voltage of a mark 0.75v 1.0v nominal pulse width 244ns 244ns t 30 t 4 t 4 t 4 t 4 t +v +v 1 ?v 0 t1818900-92 ?v 1 t 30 t 30 t 30 t 30 t 30 shaded area in which signal should be monotonic t average period of synchronizing signal XRT86VX38 45 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 f igure 4. dsx-1 p ulse t emplate ( normalized amplitude ) t able 11: dsx1 i nterface i solated pulse mask and corner points m inimum curve m aximum curve t ime (ui) n ormalized amplitude t ime (ui) n ormalized amplitude -0.77 -.05v -0.77 .05v -0.23 -.05v -0.39 .05v -0.23 0.5v -0.27 .8v -0.15 0.95v -0.27 1.15v 0.0 0.95v -0.12 1.15v 0.15 0.9v 0.0 1.05v 0.23 0.5v 0.27 1.05v 0.23 -0.45v 0.35 -0.07v 0.46 -0.45v 0.93 0.05v 0.66 -0.2v 1.16 0.05v 0.93 -0.05v 1.16 -0.05v XRT86VX38 46 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description t able 12: ac e lectrical c haracteristics vdd io = 3.3v + 5% , vdd core = 1.8v + 5%, t a =25c, unless otherwise specified p arameter s ymbol m in . t yp . m ax . u nits mclkin clock duty cycle 40 - 60 % mclkin clock tolerance - 50 - ppm XRT86VX38 47 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 86vx38 ordering information p roduct n umber p ackage o perating t emperature r ange XRT86VX38ib329 329 fine pitch ball grid array -40 ? c to +85 ? c XRT86VX38ib256 256 fine pitch ball grid array -40 ? c to +85 ? c package dimensions for 329 fine pitch ball grid array 329 fine pitch ball grid array (17.0 mm x 17.0 mm, fpbga) rev. 1.00 symbol min max min max a 0.056 0 .067 1.43 1 .71 a1 0.010 0.014 0.26 0.36 a2 0.046 0.053 1.17 1.35 d 0.663 0.675 16.85 17.15 d1 0.567 bsc 14.40 bsc b 0.014 0 .018 0.36 0 .46 e 0.031 bsc 0 .80 bsc inches millimeters note: the control dimension is in millimeter. b a e d c a1 corner f h g j k m n p l 1 32 4 5 7 8 9 10 6 d1 12 13 14 d1 d 11 d e b a1 a a2 (a1 corner feature is mfger option ) plane seating v w 18 17 15 16 15 15 15 19 r t u XRT86VX38 48 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description 4 package dimensions for 256 fine pitch ball grid array 256 fine pitch ball grid array (17.0 mm x 17.0 mm, fpbga) rev. 1.00 symbol min max min max a 0.058 0.070 1.48 1.78 a1 0.013 0.017 0.33 0.43 a2 0.045 0.053 1.15 1.35 d 0.661 0.677 16.80 17.20 d1 0.591 bsc 15.00 bsc b 0.020 0.024 0.50 0.60 e 0.039 bsc 1.00 bsc inches millimeters note: the control dimension is in millimeter. b a e d c a1 corner f h g j k m n p l 1 32 4 5 7 8 9 10 6 d1 12 13 14 d1 d 11 d e b a1 a a2 (a1 corner feature is mfger option) plane seating r t 15 16 49 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infr ingement. charts and schedules contai ned here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assuranc es to its satisfaction that: (a) th e risk of injury or damage has been minimized; (b) th e user assumes all such ris ks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2009 exar corporation datasheet june 2009. reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. XRT86VX38 octal t1/e1/j1 framer/liu combo - hardware description rev. 1.0.1 XRT86VX38 50 rev. 1.0.1 octal t1/e1/j1 framer/liu combo - hardware description p4. revision history r evision # d ate d escription 1.0.0 may. 01, 2009 initial release of hardware description 1.0.1 june 16, 2009 update packaging name to fpbga, add bits functionality to general description, updated features and applications and updates to eletrical tables |
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